In typical integrated circuit fabrication processes, heavily doped source and drain regions and lightly doped source and drain regions of metal-oxide-semiconductor devices are often formed by implanting dopants into desired regions. Conventionally, rapid thermal annealing (RTA) is used to activate the implanted ions of the dopants. The RTA technique typically includes quickly raising the temperature of a wafer and holding it at a high temperature for a time long enough to successfully perform the desired annealing.
When used for dopant activation, RTA requires exquisite control of wafer temperature because the high thermal activation energy required for the electrical activation of the dopants also adversely causes the diffusion of dopants. Advanced methods such as spike annealing, which has a high temperature-ramp rate, are thus used to shorten the duration of heating and cooling, hence minimizing the dwell time at peak temperature to nominally zero. In typical spike annealing, temperature is quickly ramped up to a high temperature. Without holding at the high temperature, the temperature of the wafer is immediately ramped down.
To satisfy the demands for forming increasingly smaller semiconductor devices, new processing and manufacturing techniques need to be developed in order to further reduce the diffusion of dopants. Accordingly, an important requirement for the new techniques is to reduce the amount of time that a semiconductor wafer is exposed to high temperatures during the activation. Flash anneal was thus introduced. In typical flash anneals, the wafers are exposed to the energy radiated by a flash lamp for a very short time, for example, several milliseconds. This significantly reduces the diffusion of dopants.
Flash anneals suffer drawbacks, however. Conventional flash anneals cannot reduce the sheet resistance of source and drain regions to a satisfactory level. This is because if sheet resistance is to be lowered, higher energies and higher anneal temperatures have to be provided. This will adversely cause the increase in wafer warpage due to the fact that a flash anneal process only provides energy to one side of a wafer. In addition, since the uniformity of flash anneal is related to the surface condition of the wafer, with the application of higher energies and higher anneal temperatures, the non-uniformity of sheet resistance on the wafer may be increased.